Improvement of the performances of integrated circuits requires an improvement to the integrated materials present. Although manufacture of the transistor (hot part of the integration) has continued to maximize the use of basic materials such as doped polycrystalline silicon and a silicon oxide grid dielectric for the last 30 years, a technological break has occurred in the choice of materials for the interconnection part. Copper has replaced aluminum for reasons of resistivity and therefore propagation of the electronic signal. Similarly, for reasons of parasite capacitance between the metallic interconnection strips, the dielectric material that for a long time was based on plasma deposited silicon oxide, has been replaced by materials with lower dielectric constant, frequently called <<Low-k>> materials (where k is the dielectric constant).
Copper is still the single choice for the conducting material for circuits far on the input side. But the dielectric material is changing, because the important parameter is to reduce its dielectric constant to reduce phenomena related to parasite capacitances created between the conducting strips.
Therefore, we have changed from a silicon oxide type material deposited by PECVD plasma techniques to materials still based on silicon, but that have a different nature more and more similar to organic structures (introduction of carbon in the monomer structure-structures —(Si—OC)——)).
Apart from the development of increasingly organic structures, introduction of porosities appears as being one of the solutions to reduce the dielectric constant of these insulating materials, the ultimate purpose being to integrate air with a dielectric constant equal to 1.
Such structures are already known in prior art; for example refer to document WO 2004/001842. This document discloses the use of an organic material that is then eliminated by thermal degradation by various physicochemical processes (plasma attack or wet chemical etching.
Different approaches are possible to make these cavities between lines, such as the use of a sacrificial material during integration that is then extracted using various physicochemical processes (plasma type attack, or wet chemical etching).
A first possibility is to use a dielectric material deposited between interconnection strips and then eliminated by thermal degradation, that may or may not be assisted by ultraviolet or electron radiation.
A second possibility consists of making a nonconforming deposit that does not entirely fill the cavity during the deposition step, thus creating an air volume.
The difficulty of known approaches is to find a sacrificial material capable of resisting integration stresses (thermal budget, mechanical stress, etc.).
Another limitation to these techniques relates to the globality of the process; the entire sacrificial material is eliminated regardless of the technique used.
In order to satisfy this problem, cavities may be defined by lithography and etching, which in this precise case addresses specific and required zones (for example creation of an air gap in dense zones only). One problem (and not the least) is that adding these steps is very expensive industrially.
Finally, and regardless of what technique is used, the creation of a good “air gap” should preferably satisfy the following criteria:                no residues left in the air gap (leakage current between lines, breakdown field between lines).        no etching of the copper and barrier layers surrounding the entire copper line, to avoid electromigration and electro corrosion phenomena.        